This invention relates generally to error detection in processing circuitry, and more particularly to enhancing error detection in processing circuitry using instruction address parity comparison.
As digital designs with processing circuitry, such as microprocessors, become more complex, demand for improved error detection is also increasing. In a microprocessor or any complex design that provides best of breed error detection, various approaches may be devised to check for possible errors caused by design flaws or single event upsets. A single event upset (SEU) is a change of state caused by a high-energy particle strike to a sensitive node in a micro-electronic device that may result from environmental effects, such as alpha particles. SEUs, as well as design flaws, can result in the unexpected changes in state. Error checking techniques in processing systems are typically localized physically, either in specific data flows, state machines, or interfaces, and therefore limited in scope of coverage. In processing circuitry with deep pipelines, better schemes to cover a wide scope of the design are desirable. As pipelined instructions advance through pipeline stages, multiple functional units within the processing circuitry may be involved in performing various tasks to determine address values for the current instruction and next instruction. These instructions addresses may be sequentially generated, or from performing a branch to its targets, or from new program start up, or interrupt conditions. Since many of the states used to perform the actual execution of a program are used to also determine the instruction address, detecting an errant address value will also indirectly capture any incorrect state that exists for other duties. An error could occur at any stage in the pipeline in any of the units and lead to further problems downstream, as future address values are modified based on an errant address value.
It would be beneficial to develop an approach to quickly identify error conditions in resulting incorrect instruction address values after instructions are passed through various functional units in processing circuitry. Accordingly, there is a need in the art for enhancing error detection in processing circuitry using instruction address parity comparison.